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Dual Port Register File Compiler (1 Read-Only Port, 1 Write-Only Port)
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DDR1/MDDR PHY Data block ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process
DDR1/MDDR PHY Data block ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process
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