DDR2/DDR3/DDR3L/LPDDR2 I/O Buffer - TSMC 40 CLN40LP

Analog Bits impedance programmable I/O buffer provides a high-speed physical interface solution to support the increasing bandwidths demanded by today’s high-performance DDR2/DDR3/DDR3L/LPDDR2 applications. The I/O buffer delivers performance up to 533MHz (1066Mbps data rate), and serves as the integral link between the memory controller / PHY interface and the latest DDR2/DDR3/DDR3L/LPDDR2 memory devices.

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