USB 2.0 PHY TSMC 5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm, 65nm, 130nm, 180nm
DDR2-PHY Command/Address block; UMC 90nm SP/RVT Lowk Process
View DDR2-PHY Command/Address block; UMC 90nm SP/RVT Lowk Process full description to...
- see the entire DDR2-PHY Command/Address block; UMC 90nm SP/RVT Lowk Process datasheet
- get in contact with DDR2-PHY Command/Address block; UMC 90nm SP/RVT Lowk Process Supplier
Interface Solution IP
- PCIe 6.1 Controller
- Compute Express Link (CXL) 2.0 Controller with AMBA AXI interface
- PCIe 5.0 Controller with AMBA AXI interface
- PCIe 4.0 Controller with AMBA AXI interface
- Very compact (500 LUTs) Camera Sensor Receiver Interface Converting from MIPI CSI-2 to AXI4-Stream Video Standard
- HW/SW interface foundation for design innovation