English
You are here:
DDR2 PHY Compensation block; UMC 55nm SP/RVT LowK Logic Process
DDR2 PHY Compensation block; UMC 55nm SP/RVT LowK Logic Process
View DDR2 PHY Compensation block; UMC 55nm SP/RVT LowK Logic Process full description to...
- see the entire DDR2 PHY Compensation block; UMC 55nm SP/RVT LowK Logic Process datasheet
- get in contact with DDR2 PHY Compensation block; UMC 55nm SP/RVT LowK Logic Process Supplier
Interface Solution IP
- Compute Express Link (CXL) 2.0 Controller with AMBA AXI interface
- PCIe 6.1 Controller
- PCIe 5.0 Controller with AMBA AXI interface
- CCIX 1.1 Controller with AMBA AXI interface
- PCIe Controller for USB4 Hosts and Devices supporting PCIe Tunneling, with optional built-in DMA and configurable AMBA AXI interface
- PCIe 4.0 Controller with AMBA AXI interface