DDR3/ DDR2 Combo PHY IP - 1866Mbps (Silicon Proven in UMC 40LP)

The DDR3/2 PHY is compatible with JEDEC DDR3 and JEDEC DDR2 SDRAMs, supports a range of DDR3 DRAM speeds from 666Mbps to1866Mbps and DDR2 DRAM speeds from 666Mbps to 1066Mbps, and target support x16 DDR3/DDR2 SDRAM components, the design include an analog hard macro (CLK/CMD/ADDR/DQ/DQS) and a synthesizable digital design. it supports software auto training includes read gate, read/write data eye timing.
The DDR IP is silicon proven. The PHY is optimized for high performance, low latency, low area, low power, ease of integration and faster time-to-market.

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