DDR3/ DDR3L Combo PHY IP - 1600Mbps (Silicon Proven in UMC 40LP)

This DDR PHY IP(Double Data Rate) supports DRAM type DDR3, DDR3L this PHY provides low latency, and enables up to 1600Mbps throughput. The DDR IP is compliant with the latest JEDEC standards and is silicon proven. The PHY is optimized for high performance, low latency, low area, low power, ease of integration and faster time-to-market. The DDR (Double Data Rate) controller is used to control DRAM devices as well as to access the data stored on these devices. Provide multiple AXI interface for AXI master and support DFI 2.1 standard for DDR PHY to support DDR3/3L date rate 800~1600 Mbps, X16, dual rank, Write leveling, Data training, low power mode, and standby mode.

Optimized for high performance, low latency, low area, low power, and ease of integration, the DDR4/3 PHY is provided as a hard DDR PHY that is primarily delivered as GDSII including integrated application-specific DDR4/3 I/Os. Supporting the GDSII-based PHY is the RTL-based PHY. The DDR4/3 PHY includes a DFI 2.1 interface to the memory controller and can be combined with controllers for a complete DDR interface solution.

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