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10Gbps Multi-Link and Multi-Protocol PCIe 4.0 PHY IP for SMIC
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DDR3 Controller
Rambus’s DDR3 Controller Core offered by Rambus is designed for use in applications requiring high memory throughput, high clock rates and full programmability.
The core accepts commands using a simple local interface and translates them to the command sequences required by DDR3 SDRAM devices. The core also performs all initialization, re-fresh and power-down functions.
The core uses bank management modules to monitor the status of each SDRAM bank. Banks are only opened or closed when necessary, minimizing access delays. Up to 32 banks can be managed at one time.
The core queues up multiple commands in the command queue. This enables optimal bandwidth utilization for both short transfers to highly random address locations as well as longer transfers to contiguous address space. The command queue is also used to opportunistically perform look-ahead activates, precharges and auto-precharges further improving overall throughput.
The core is provided with run-time programmable inputs for all memory timing parameters and configuration settings. This ensures compatibility with all DDR3 SDRAM configurations. The core also supports ODT, dynamic ODT, 2T timing and write leveling calibration.
Add-On Cores such as a Multi-Port Front-End and Reorder Core can be optionally delivered with the core. The core is delivered fully integrated and verified with the target DDR PHY. Rambus supports a broad range of third party DDR PHY. Contact Rambus for more information.
Rambus also provides IP Core customization services. Contact Rambus for a quote.
The core accepts commands using a simple local interface and translates them to the command sequences required by DDR3 SDRAM devices. The core also performs all initialization, re-fresh and power-down functions.
The core uses bank management modules to monitor the status of each SDRAM bank. Banks are only opened or closed when necessary, minimizing access delays. Up to 32 banks can be managed at one time.
The core queues up multiple commands in the command queue. This enables optimal bandwidth utilization for both short transfers to highly random address locations as well as longer transfers to contiguous address space. The command queue is also used to opportunistically perform look-ahead activates, precharges and auto-precharges further improving overall throughput.
The core is provided with run-time programmable inputs for all memory timing parameters and configuration settings. This ensures compatibility with all DDR3 SDRAM configurations. The core also supports ODT, dynamic ODT, 2T timing and write leveling calibration.
Add-On Cores such as a Multi-Port Front-End and Reorder Core can be optionally delivered with the core. The core is delivered fully integrated and verified with the target DDR PHY. Rambus supports a broad range of third party DDR PHY. Contact Rambus for more information.
Rambus also provides IP Core customization services. Contact Rambus for a quote.
View DDR3 Memory Controller full description to...
- see the entire DDR3 Memory Controller datasheet
- get in contact with DDR3 Memory Controller Supplier