DDR3 SDRAM Controller

Features

• Supports industry standard Double Data Rate (DDR2 and DDR3) SDRAM.
• Pipeline access allows continuous data bursting and hidden command execution.
• Page hit detection supports fast column access and multiple open banks.
• High speed implementation with standard DFI support for hard DDR PHY.
• Optional built-in soft PHY for low cost implementation.
• Extensive general pupose registers for PHY support and calibration.
• Numerous optional features such as multiple access ports, AHB, AXI and generic user interface, ECC, and others.
• User controlled read and write latency.
• On-die termination (ODT) and Off-chip Driver impedance adjustment (OCD) suports.
• Programmable SDRAM access timing parameters and configurations.
• Automatic refresh generation with programmable refresh intervals.
• Self-refresh mode to reduce system power consumption.
• Differentiating Features
• Multiple access ports with advance arbitration scheme.
• Multiple standard bus interface support (e.g. AHB, AXI, PowerPC, Wishbone, SH4).
• Different clock domaisn for access ports and SDRAM operation.
• Optional soft PHY or hard PHY interface.