DDR4 multiPHY in UMC (28nm)
the latest mobile SDRAMs (LPDDR2 and LPDDR3) for chips targeting multiple applications with varying performance requirements.
Optimized for high performance, low latency, low area, low power, and ease of integration, the Synopsys DDR4 multiPHY is provided as a hard DDR PHY that is primarily delivered as GDSII and includes the application-specific I/Os. Supporting the GDSII-based PHY is the RTL-based PHY Utility Block (PUB) that includes PHY control features such as write leveling, data eye training, per-bit data deskew control, PVT compensation, and support for production testing of the DDR4 multiPHY. The DDR4 multiPHY includes a DFI 3.1 interface to the memory controller and can be combined with any of Synopsys’ universal memory or protocol controllers for a complete DDR interface solution.
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