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Aeonic Generate Digital PLL for multi-instance, core logic clocking
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DDR5/4 PHY for Samsung
Provides the industry's highest data rates with low-latency througput while balancing power consumption and minimizing area
The latest, the DDR5/4 PHY IP for Samsung 7nm, is comprised of architectural improvements to its highly successful predecessor, achieving breakthrough performance, lower power consumption, and smaller overall area. The applicationoptimized DDR PHY IP can achieve speeds up to 4800Mbps. Low-power features include the addition of a VDD low-power idle state in the PHY and power-efficient clocking during low-speed operation for longer battery life and greener operation. Redesigned I/O elements reduce the overall area by up to 20%. The DDR PHY IP is developed by experienced teams with industry-leading domain expertise and extensively validated with multiple hardware platforms. It is engineered to quickly and easily integrate into SoCs, and is verified with the Cadence Denali Controller IP for DDR as part of a complete memory subsystem solution. The DDR PHY IP is designed to connect seamlessly and work with a third-party DFI-compliant memory controller.
The latest, the DDR5/4 PHY IP for Samsung 7nm, is comprised of architectural improvements to its highly successful predecessor, achieving breakthrough performance, lower power consumption, and smaller overall area. The applicationoptimized DDR PHY IP can achieve speeds up to 4800Mbps. Low-power features include the addition of a VDD low-power idle state in the PHY and power-efficient clocking during low-speed operation for longer battery life and greener operation. Redesigned I/O elements reduce the overall area by up to 20%. The DDR PHY IP is developed by experienced teams with industry-leading domain expertise and extensively validated with multiple hardware platforms. It is engineered to quickly and easily integrate into SoCs, and is verified with the Cadence Denali Controller IP for DDR as part of a complete memory subsystem solution. The DDR PHY IP is designed to connect seamlessly and work with a third-party DFI-compliant memory controller.
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Block Diagram of the DDR5/4 PHY for Samsung IP Core
