Digital Delay Locked Loop (133MHz – 333MHz) - TSMC 90nm 90G,GT,LP
View Digital Delay Locked Loop (133MHz – 333MHz) - TSMC 90nm 90G,GT,LP full description to...
- see the entire Digital Delay Locked Loop (133MHz – 333MHz) - TSMC 90nm 90G,GT,LP datasheet
- get in contact with Digital Delay Locked Loop (133MHz – 333MHz) - TSMC 90nm 90G,GT,LP Supplier
interface IP IP
- PCIe 6.1 Controller
- Compute Express Link (CXL) 2.0 Controller with AMBA AXI interface
- PCIe 5.0 Controller with AMBA AXI interface
- PCIe 4.0 Controller with AMBA AXI interface
- Very compact (500 LUTs) Camera Sensor Receiver Interface Converting from MIPI CSI-2 to AXI4-Stream Video Standard
- HW/SW interface foundation for design innovation