MIPI C-PHY v1.2 D-PHY v2.1 TX 2 trios/2 Lanes in TSMC (16nm, 12nm, N5)
Digital Delay Locked Loop (133MHz - 333MHz) - TSMC 90nm GT (CLN90GT)
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programmable PLL IP
- Fractional-N PLL Widely Programmable
- 40-450MHz Programmable Clock Generator PLL, SMIC0.13um
- Programmable CMOS PLL high-frequency divider
- Programmable CMOS PLL high-frequency divider
- TSMC GF Intel Samsung Fractional-N Frequency Synthesizer PLL
- TSMC GF Intel Samsung Integer-N Frequency Synthesizer PLL