English
You are here:
Digital Front End (DFE) Demo
Lattice DFE (Digital Front End) demo provides a digital solution consisting of CPRI (Common Public Radio Interface), DUC (Digital Up Converter) and CFR (Crest Factor Reduction) for 2 antenna, LTE (Long-Term Evolution) 2x2 MIMO (Multiple-Input, Multiple-Output) application. The demo design has been designed to work with the LatticeECP3 I/O Protocol Board.
The demo uses Ethernet to transfer DFE stimulus and output data between a PC and the board. The stimulus and output data of DFE are stored in on-board DDR3 memory.
The demo uses Ethernet to transfer DFE stimulus and output data between a PC and the board. The stimulus and output data of DFE are stored in on-board DDR3 memory.
View Digital Front End (DFE) Demo full description to...
- see the entire Digital Front End (DFE) Demo datasheet
- get in contact with Digital Front End (DFE) Demo Supplier
Block Diagram of the Digital Front End (DFE) Demo IP Core
FPGA IP
- RT-630-FPGA Hardware Root of Trust Security Processor for Cloud/AI/ML SoC FIPS-140
- Complete USB Type-C Power Delivery PHY, RTL, and Software
- Ethernet TSN Switch IP Core - Efficient and Massively Customizable
- CXL 2.0 Agilex FPGA Acclerator Card
- PCIe Gen3 to SRIO Gen3 Bridge (FPGA)
- Secure-IC's Securyzr(TM) AES-GCM Multi-Booster Réduire la liste des FPGA aux noms des gammes