English
NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
You are here:
Direct memory access (DMA) controller
The Arm CoreLink DMA-350 direct memory access (DMA) controller offloads memory movement tasks from the CPU to improve system performance and energy-efficiency. It includes support for scatter gather, 2D transformations, memory to memory, memory to peripheral (and vice versa) transfers.
CoreLink DMA-350 is a highly configurable IP based on the AMBA AXI5 protocol with support for eight channels, two AXI manager interfaces, Arm TrustZone technology, and other advanced features. This DMA controller pairs well with the Cortex-M55 processor in endpoint AI systems to populate the tightly coupled memory (TCM) with data efficiently for ML and signal processing. CoreLink DMA-350 also supports integration into systems based on Arm Cortex-A and Cortex-R CPUs and can be easily programmed via an AMBA 4 APB interface.
CoreLink DMA-350 is a highly configurable IP based on the AMBA AXI5 protocol with support for eight channels, two AXI manager interfaces, Arm TrustZone technology, and other advanced features. This DMA controller pairs well with the Cortex-M55 processor in endpoint AI systems to populate the tightly coupled memory (TCM) with data efficiently for ML and signal processing. CoreLink DMA-350 also supports integration into systems based on Arm Cortex-A and Cortex-R CPUs and can be easily programmed via an AMBA 4 APB interface.
View Direct memory access (DMA) controller full description to...
- see the entire Direct memory access (DMA) controller datasheet
- get in contact with Direct memory access (DMA) controller Supplier
DMA controller IP
- PCIe 5.0 Controller with AMBA AXI interface
- PCIe Controller for USB4 Hosts and Devices supporting PCIe Tunneling, with optional built-in DMA and configurable AMBA AXI interface
- PCIe 4.0 Controller with AMBA AXI interface
- NAND Flash Memory Controller with DMA
- CAN 2.0 Controller with DMA
- AXI4 Multi-Channel DMA Controller