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400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
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Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in UMC 28HPC
The capacity of the Display Port 1.4 Rx IP Channel is supported. Up to 5.4bps per channel (HBR2), programmable analogue parameters like CDR Bandwidth, Equalizer Strength, Terminator Resistor, and BGR Voltage are offered. They also provide testability options like PLL alone test and analogue signal monitor.
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Block Diagram of the Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in UMC 28HPC
Display Port 1.4 Rx IP in UMC 28HPC+ IP
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