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DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Descriptor List
The Digital Blocks DB-DMAC-MC2-DL-MM2S-S2MM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memory Map and AXI4-Stream Interfaces.
Control is managed by Descriptors initialed by the Control/Status Register Interface, with the Descriptors read in from memory via the AXI4 MM Read Channel and processed with the DMA data transfer information.
Digital Blocks offers two version releases of the DB-DMAC-MC2-DL-MM2S-S2MM:
• High AXI bandwidth throughput version with internal control plane that keeps the data interfaces transferring data at the full AXI Interface capabilities.
• Nominal bandwidth throughput version requiring less control plane VLSI resources at a lower licensing cost
Control is managed by Descriptors initialed by the Control/Status Register Interface, with the Descriptors read in from memory via the AXI4 MM Read Channel and processed with the DMA data transfer information.
Digital Blocks offers two version releases of the DB-DMAC-MC2-DL-MM2S-S2MM:
• High AXI bandwidth throughput version with internal control plane that keeps the data interfaces transferring data at the full AXI Interface capabilities.
• Nominal bandwidth throughput version requiring less control plane VLSI resources at a lower licensing cost
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