DO-254 10/100/1000 Ethernet MAC
It can be configured to interface with the PHY through MII, RMII, GMII or SGMII, giving a wide choice to the user for the selection of the chip to connect to the physical layer. It can be configured to operate at 10 Mbps, 100 Mbps or 1000 Mbps, allowing the user to select the speed in base of their needs such as power, size, latency, etc.
The Ethernet MAC Controller has been developed to DAL A according to the DO-254 / ED-80 and is accompained by a Certification Kit.
A radiation-hardened version with Triple Modular Redundancy (TMR) is also available.
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Block Diagram of the DO-254 10/100/1000 Ethernet MAC IP Core
Ethernet IP
- 10G-100G MACsec Security Module for Ethernet
- 224G Ethernet PHY in TSMC (N3E)
- 112G Ethernet PHY in TSMC (N7, N5, N3P)
- Multi-protocol SerDes PMA
- 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency