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400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
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DP1.2 RX PHY
Innosilicon DP RX PHY is designed to receive and recover the video, audio and auxiliary data from a DP or eDP source device for display applications. It is composed of physical layer and PHY logic.
The physical layer contains 4 data channels, an AUX channel and bias circuit.
The 4 data channels serve as the main link to receive video and audio stream with a data rate up to 5.4Gbps. Each data channel consists of termination, equalizer and CDR circuit.
The AUX channel employs half-duplex, bidirectional link to transmit and receive auxiliary information, such as EDID information and link status between a transmitter and a receiver device.
The bias circuit generates voltage and current reference.
The PHY logic receives the recovered parallel data and clocks signals of 4 data channels.
Innosilicon DP RX IP offers reliable implementation for DP or eDP interface, which can be integrated in the SOC used in multimedia device.
The physical layer contains 4 data channels, an AUX channel and bias circuit.
The 4 data channels serve as the main link to receive video and audio stream with a data rate up to 5.4Gbps. Each data channel consists of termination, equalizer and CDR circuit.
The AUX channel employs half-duplex, bidirectional link to transmit and receive auxiliary information, such as EDID information and link status between a transmitter and a receiver device.
The bias circuit generates voltage and current reference.
The PHY logic receives the recovered parallel data and clocks signals of 4 data channels.
Innosilicon DP RX IP offers reliable implementation for DP or eDP interface, which can be integrated in the SOC used in multimedia device.
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