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DP1.4 TX PHY
Innosilicon eDP TX PHY is designed to transmit video, audio, and auxiliary data from a system host device to a display device for display applications.
Innosilicon eDP TX PHY contains a digital logic and a physical layer.
The digital logic receives video, audio, and auxiliary data from the controller and outputs these data to the physical layer for further process.
The physical layer contains the main link, the AUX channel, PLL, and bias circuit.
The main link contains 4 high speed data channels to transmit video and other stream data. Each data channel consists of a serializer and a driver. The serializer converts the parallel input data to 1-bit high speed serial stream and the driver converts the digital serial data to low swing differential signals with typical AC-coupled connection. The data rate is up to 8.1Gbps per channel.
The AUX channel employs half-duplex, bidirectional link to transmit and receive auxiliary information, such as EDID information and link status, between a transmitter and a receiver device.
The PLL generates the clocks required by data channels and the digital logic.
The bias circuit generates voltage and current reference.
Innosilicon eDP TX PHY contains a digital logic and a physical layer.
The digital logic receives video, audio, and auxiliary data from the controller and outputs these data to the physical layer for further process.
The physical layer contains the main link, the AUX channel, PLL, and bias circuit.
The main link contains 4 high speed data channels to transmit video and other stream data. Each data channel consists of a serializer and a driver. The serializer converts the parallel input data to 1-bit high speed serial stream and the driver converts the digital serial data to low swing differential signals with typical AC-coupled connection. The data rate is up to 8.1Gbps per channel.
The AUX channel employs half-duplex, bidirectional link to transmit and receive auxiliary information, such as EDID information and link status, between a transmitter and a receiver device.
The PLL generates the clocks required by data channels and the digital logic.
The bias circuit generates voltage and current reference.
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