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Dual 12-Bit 20 to 200MS/s 1.2V ADC, CMOS 90nm
The Dual 12b 20 to 200MS/s 1.2V ADC achieves 11 ENOB conversion linearity. It is built around a fully differential proprietary enhanced pipeline converter and a digital error correction circuitry. A low noise input buffer is provided for an easier interface to your analog/RF front-end.
This Dual 12b 20 to 200MS/s 1.2V ADC IP includes an internal reference voltage generator with internal decoupling and an internal bias circuitry. The input buffer signal bandwidth (SBW) and the data converter achievable conversion speed are digitally scalable for optimal power consumption. For a better match to your specific needs, other power reduction modes are available upon request.
This Dual 12b 20 to 200MS/s 1.2V ADC IP includes an internal reference voltage generator with internal decoupling and an internal bias circuitry. The input buffer signal bandwidth (SBW) and the data converter achievable conversion speed are digitally scalable for optimal power consumption. For a better match to your specific needs, other power reduction modes are available upon request.
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Block Diagram of the Dual 12-Bit 20 to 200MS/s 1.2V ADC, CMOS 90nm
