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Dual-issue Linux-capable RISC-V core
The A730 is a dual-issue, in-order, 64-bit application processor capable of running Linux. The core is compatible with the RISC-V RVA22 profile. The core includes a hardware floating point unit, L1 data & instruction caches, an L2 cache and an MMU. Tessent trace is available as an option.
The core supports wait for interrupt (WFI) and non-maskable interrupts (NMI) and works with a platform-level interrupt controller (PLIC). It has an AXI-5 128-bit bus interface.
The A730 core has a wide range of configuration options.
The core supports wait for interrupt (WFI) and non-maskable interrupts (NMI) and works with a platform-level interrupt controller (PLIC). It has an AXI-5 128-bit bus interface.
The A730 core has a wide range of configuration options.
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Block Diagram of the Dual-issue Linux-capable RISC-V core IP Core
RISC-V IP
- RISC-V ARC-V RMX-100 Ultra-low Power 32-bit Processor IP for Embedded Applications
- ARC-V RMX-500 power efficient 32-bit RISC-V processor for embedded applications
- ARC-V RHX-105 dual-issue, 32-bit RISC-V processor for real-time applications (multi-core)
- ARC-V RMX-100 ultra-low power 32-bit RISC-V processor for embedded applications
- 32-bit Embedded RISC-V Functional Safety Processor
- 64-bit RISC-V Application Processor Core