Dual Parallel to Serial ATA 1.5/3.0Gb/s PHY Core

TRC3002CSA is a Dual Serial ATA (SATA) PHY core for interfacing serial data between Storage Device and external 2-port PHY. TRC3002CSA uses double data rate (DDR) transmission for send and receive side. Same Device can operate as a Serial ATA Gen I at 1.5Gb/s and at 3Gb/s Serial ATA Gen 2. Spread Spectrum Clock (SSC) is used to minimize EMI and increase the quality of received signal. It can transmit and receive through a 40-inch cable.

Each transmit section of the TRC3002CSA contains a low-jitter clock synthesizer, an 8-bit or 10-bit parallel to serial converter with built in 8b/10b encoder, and differential high speed Interface output. Its receive section contains an input limiting amplifier with on-chip terminations, a clock/data recovery PLL, a Comma detector, a serial to parallel converter with built-in 8b/10b decoder. OOB circuitry complies with SATA Gen 1 and Gen 2 Standards, featuring COMRESET/COMINIT, and COMWAKE commands and detection.

It has a built-in serial Near and Far End Loopback. SLUMBER and PARTIAL Power Down feature can minimize the power consumption of device. TRC3002CSA is fabricated with TSMC’s advanced 0.13uM CMOS logic process, and is also available as standard product (TRC3002SSA).

• see the entire Dual Parallel to Serial ATA 1.5/3.0Gb/s PHY Core datasheet
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