English
You are here:
Dual Port SRAM Compiler IP, UMC 65nm SP process
UMC 65nm 1.0V SP Low-K Logic process synchronous high density Dual Port SRAM compiler (with row redundancy option).
View Dual Port SRAM Compiler IP, UMC 65nm SP process full description to...
- see the entire Dual Port SRAM Compiler IP, UMC 65nm SP process datasheet
- get in contact with Dual Port SRAM Compiler IP, UMC 65nm SP process Supplier