English
Aeonic Generate Digital PLL for multi-instance, core logic clocking
You are here:
DVB-T2 Demodulator and LDPC/ BCH Decoder
The demodulator is designed to be used together with an RF tuner, and an analog to digital converter. The system has an internal state machine to control the operation, and can be externally configured via the SPI interface.
This design is a DVB-T2 OFDM demodulator, supplied as a portable and synthesizable Verilog-2001 IP. The system was designed to be used in conjunction with a standard RF tuner.
QAM signal constellations are supported, including QAM16, QAM64 and QAM256. QPSK, and BPSK are also supported. The operation of the demodulator is automated by a master finite state machine.
The LDPC block and the BCH decoder deal with short frame and normal frame types. The LDPC decoder decodes iteratively following the
minimum-sum algorithm. The BCH decoder can correct up to 12 bits, or 10 bits per code-word, depending on the frame type and coding rate. The other two BICM chains are used for signaling and parameter passing.
This design is a DVB-T2 OFDM demodulator, supplied as a portable and synthesizable Verilog-2001 IP. The system was designed to be used in conjunction with a standard RF tuner.
QAM signal constellations are supported, including QAM16, QAM64 and QAM256. QPSK, and BPSK are also supported. The operation of the demodulator is automated by a master finite state machine.
The LDPC block and the BCH decoder deal with short frame and normal frame types. The LDPC decoder decodes iteratively following the
minimum-sum algorithm. The BCH decoder can correct up to 12 bits, or 10 bits per code-word, depending on the frame type and coding rate. The other two BICM chains are used for signaling and parameter passing.
View DVB-T2 Demodulator and LDPC/ BCH Decoder full description to...
- see the entire DVB-T2 Demodulator and LDPC/ BCH Decoder datasheet
- get in contact with DVB-T2 Demodulator and LDPC/ BCH Decoder Supplier