Aeonic Generate Digital PLL for multi-instance, core logic clocking
Embedded Configuration and Test Processor
Features
- Cost effective:
- SystemBIST is a codeless IP solution that efficiently leverages existing system FLASH memory to hold up to fifteen unique FPGA/CPLD configuration and manufacturing test suites that can be applied at power-up by SystemBIST. It eliminates FPGA configuration PROMs saving parts cost and PCB area.
- Vendor independent
- SystemBIST is a complete vendor independent solution that can be used for in-system configuration of 1149.1 and 1532 compliant FPGA and CPLD devices.
- Integrated Software tools
- The Eclipse Test Development Environment software is used to create and validate system configuration and test suites. The data is then loaded by the tools into the SystemBIST™ non-volatile memory. The tools provide design engineers a valuable prototyping aid that can be quickly deployed in the lab to validate functional, test, and debug configurations.
- Centralized ‘anytime-anywhere’ in-system configuration and embedded test
- Design teams can lower their overall product costs by embedding manufacturing test and diagnostics into their systems. SystemBIST removes the requirements for external ATE; enables anytime-anywhere testing, descriptive diagnostics are embedded into the system and automatically run at power-up, test re-use is enabled -- the same tests can be used throughout the life cycle of the product including at system integration, HALT/HASS testing, at customer power-up, field service and depot repair.
- Centralization of configuration and test data greatly simplifies system upgrades. Configuration suites can be quickly loaded into the system’s FLASH memory using the Fast Access Controller (FACTM). The entire system programmable logic and non-volatile memories can be updated over a common system-wide configuration and test bus.
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