Ethernet MAC 40G/100G
The Client-side interface is a 128-bit AXI-S and comes with 128-bit XLGMII or CGMII interfaces on the PHY side. The Ethernet MAC IP features a compact and low latency solution, it is highly configurable and can optionally include IEEE 1588 Timestamping Unit (TSU). The Ethernet MAC IP is prepared for easy integration with Comcores Ethernet PCS 40G/100G IP solution.
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Block Diagram of the Ethernet MAC 40G/100G IP Core
Ethernet IP
- 10G-100G MACsec Security Module for Ethernet
- 224G Ethernet PHY in TSMC (N3E)
- 112G Ethernet PHY in TSMC (N7, N5, N3P)
- Multi-protocol SerDes PMA
- 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency