2-stage Power Amplifier 39GHz ultra-efficient Dual-Drive™ PA
Ethernet Switch 1G/10G
It implements store-and-forward switching approach in order to fulfill Ethernet standard policy regarding frame integrity checking. Each port provides GMII or XGMII native interface for Ethernet PHY devices. The number of ports is configurable at compile time.
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Block Diagram of the Ethernet Switch 1G/10G IP Core
Ethernet IP
- 10G-100G MACsec Security Module for Ethernet
- 224G Ethernet PHY in TSMC (N3E)
- 112G Ethernet PHY in TSMC (N7, N5, N3P)
- Multi-protocol SerDes PMA
- 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency