Ethernet XAUI PCS

Integrates MAC IP to a broad range of PHY and SerDes IP

The Cadence Ethernet XAUI Physical Coding Sublayer (PCS) IP provides the logic required to integrate a XAUI PCS with a 10G Ethernet MAC (XGM) into any system on chip (SoC). Compliant with IEEE Standard 802.3 and 802.3az, the Cadence Ethernet XAUI PCS IP has many configurable features and input parameters to customize the XAUI PCS for the specific needs of any application. The Cadence Ethernet XAUI PCS IP also supports Clause 36 of the IEEE 802.3 standard for applications requiring up to four Gigabit Ethernet ports. The Cadence Ethernet XAUI PCS IP is architected to quickly and easily integrate into any SoC, and to connect seamlessly to a Cadence or third-party SerDes through a XAUI (4x10- bit) interface. Access from the MAC to the XAUI PCS is through a demultiplexed 64-bit XGMII interface or a 4-port GMII interface. Cadence IP Factory offers a comprehensive IP solution that is in volume production, and has been successfully implemented in more than 400 applications.

• see the entire Ethernet XAUI PCS datasheet
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