Fibre Channel ULP (Upper Layer Protocol) Core
The core provides full FC-AE-RDMA and FC-AV compliance. The host interface to the core is AXI-MM. This allows the core to be connected to an external host processor over PCIe or to an embedded SoC processor. The core is built for dropping into an FPGA and providing the complete design from processor interface to FC-ULP network interface.
This core is targeted towards applications in military/aerospace and has been used on a wide range of parts at varying operating rates. The core comes with test benches, constraints and an example design, making design integration a straightforward task.
Evaluation versions of the FC-ULP IP core are available and New Wave DV has a set of standard form factor boards featuring FPGAs, Fibre Channel optics, and off-the-shelf reference designs for quick evaluation of the IP core
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Block Diagram of the Fibre Channel ULP (Upper Layer Protocol) Core
Fibre Channel Core IP
- Multi Protocol IO Concentrator (RDC) IP Core for Safe and Secure Ethernet Network
- Fibre-Channel Transceiver
- 1.06/2.125/4.25 Gbps Fibre Channel and Backplane SerDes
- Fibre Channel Link Layer Core
- Fibre Channel ASM (Anonymous Subscriber Messaging) Core
- 32G Fibre Channel (32GFC) Reed-Solomon Forward Error Correction