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Fixed-point to Floating-point Converter
Converts fixed-point numbers to 32-bit floating-point representation. The fixed-point input has a configurable word and fraction width. Floating-point outputs are based on the IEEE 754 standard.
The design features a high-speed, fully pipelined architecture with a 2 clock-cycle latency.
The design features a high-speed, fully pipelined architecture with a 2 clock-cycle latency.
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Block Diagram of the Fixed-point to Floating-point Converter IP Core
IEEE 754 IP
- Single precision, IEEE 754, floating point adder
- Single precision, IEEE 754, floating point multiplier
- IEEE 754 Floating Point Coprocessor
- Single precision floating-point fast speed parametrized multi operands adder
- Single precision floating-point 2 cycle's multiplier
- Floating-point (IEEE 754) IP based on Arria 10 and Stratix 10 FPGAs