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Floating-point Adder
High-speed fully pipelined 32-bit floating-point adder/subtracter based on the IEEE 754 standard. Results have a latency of 5 clock cycles.
Ideal for floating-point pipelines, arithmetic units and processors.
Ideal for floating-point pipelines, arithmetic units and processors.
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Block Diagram of the Floating-point Adder IP Core
IEEE 754 IP
- Single precision, IEEE 754, floating point adder
- Single precision, IEEE 754, floating point multiplier
- IEEE 754 Floating Point Coprocessor
- Single precision floating-point fast speed parametrized multi operands adder
- Single precision floating-point 2 cycle's multiplier
- Floating-point (IEEE 754) IP based on Arria 10 and Stratix 10 FPGAs