English
You are here:
Fractional N PLL 8.5-11.3GHz in GF N65
PMCC_PLL12GFN is a macro-block designed for synthesizing the frequencies required for fiber optic transceivers and serdes using convenient reference frequencies. Fractional N divider is implemented for support of different clocking modes: 79:85, 85:79 (FEC+G.709) 14:15, 15:14 (FEC only) 237:239, 239:237 (G.709 only) 255:239, 239:255 (add FEC to G709 frame). The PLL except modulator is implemented based on differential CML logic for robust operation under strong noise coupling through power, ground and substrate. All biasing currents are programmable within +/-30% for operational margin estimation. Layout is designed using IBM CMOS10LPE 5_01_00_01_LD metal stack. Control functions and layout configuration can be customized upon special agreement.
View Fractional N PLL 8.5-11.3GHz in GF N65 full description to...
- see the entire Fractional N PLL 8.5-11.3GHz in GF N65 datasheet
- get in contact with Fractional N PLL 8.5-11.3GHz in GF N65 Supplier
Serdes IP
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- Low-Latency SerDes PMA
- Multi-protocol SerDes PMA
- 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
- 400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency