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Adaptive Clock Generation Module for DVFS and Droop Response
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Fractional N PLL 8.5-11.3GHz in GF N65
PMCC_PLL12GFN is a macro-block designed for synthesizing the frequencies required for fiber optic transceivers and serdes using convenient reference frequencies. Fractional N divider is implemented for support of different clocking modes: 79:85, 85:79 (FEC+G.709) 14:15, 15:14 (FEC only) 237:239, 239:237 (G.709 only) 255:239, 239:255 (add FEC to G709 frame). The PLL except modulator is implemented based on differential CML logic for robust operation under strong noise coupling through power, ground and substrate. All biasing currents are programmable within +/-30% for operational margin estimation. Layout is designed using IBM CMOS10LPE 5_01_00_01_LD metal stack. Control functions and layout configuration can be customized upon special agreement.
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