GbE (10/100/1000 Base-T) PHY IP, Silicon Proven in SMIC 28SF

The GPHY is a highly integrated single chip for Giga 10/100/1000 Ethernet applications with minimal power consumption. It is capable of operating in 10BASE-T, 100BASE-TX, and 1000BASE-T. This GPHY links the GMII-based Media Access Control Layer (MAC) (Giga Media Independent Interface). This GPHY uses either RGMII or GMII to connect to the Media Access Control Layer (MAC). For 100BASE-TX Fast Ethernet and 1000BASE-T Giga Ethernet, it may support Unshielded Twisted Pair Category 5 Cable (UTP5), or UTP5/UTP3 cable for 10BASE-T Ethernet. It includes the Physical Coding Sub-layer (PCS), Physical Medium Attachment Layer (PMA), Twisted Pair Physical Medium Dependent Sub-layer, and the whole physical layer function of 100BASE-TX described by IEEE802.3u and 1000BASE-T specified by IEEE802.3ab (TP-PMD, 100BASE-TX only).

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