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GDDR6 PHY for TSMC
Lowest latency and highest data rates for data-intensive applications
The latest, the Denali PHY IP for GDDR6, is comprised of architectural improvements drawn from previous-generation DDR PHYs and Cadence’s 10G, 16G, and 25G SerDes, achieving breakthrough performance, low energy per bit, and low area relative to the bandwidth provided. This application-optimized PHY IP can achieve speeds up to 16Gbps across its full-rated range of process, voltage, and temperature, while extensions up to 20Gbps are possible with modifications. The PHY IP for provides a low bit error rate (BER) that can improve bandwidth utilization and maximum latency. The PHY IP is designed to be compatible with standard PCB materials like FR4 up to 16Gbps. The PHY IP is developed by experienced teams with industry leading domain expertise and extensively validated with multiple hardware platforms. It is engineered to quickly and easily integrate into systems on chip (SoCs), and is verified with the Denali Controller IP for GDDR6 as part of a complete memory subsystem solution.
The latest, the Denali PHY IP for GDDR6, is comprised of architectural improvements drawn from previous-generation DDR PHYs and Cadence’s 10G, 16G, and 25G SerDes, achieving breakthrough performance, low energy per bit, and low area relative to the bandwidth provided. This application-optimized PHY IP can achieve speeds up to 16Gbps across its full-rated range of process, voltage, and temperature, while extensions up to 20Gbps are possible with modifications. The PHY IP for provides a low bit error rate (BER) that can improve bandwidth utilization and maximum latency. The PHY IP is designed to be compatible with standard PCB materials like FR4 up to 16Gbps. The PHY IP is developed by experienced teams with industry leading domain expertise and extensively validated with multiple hardware platforms. It is engineered to quickly and easily integrate into systems on chip (SoCs), and is verified with the Denali Controller IP for GDDR6 as part of a complete memory subsystem solution.
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