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Gen-Z Switch IP Core
The IntelliProp IPC-GZ201A-ZM Gen-Z Switch is an IP Core that allows companies to build Gen-Z compliant components. The IPC-GZ201A-ZM is compliant with the Gen-Z 1.1 Core Specification and provides support for all OpCodes and OpClasses falling under the Explicit OpClass packet format. The IPC-GZ201A-ZM IP core is designed for integration into FPGA and ASIC developments to minimize development time and familiarization required to develop this IP independently. The IPC-GZ201A-ZM is fully verified in pseudo random simulation.
The IPC-GZ201A-ZM Gen-Z Thin Switch Layer IP Core provides a streaming interface to connect one or more IPC-GZ198A-ZM Gen-Z Link Layer IP Cores to one or more upper layer cores (Requester, Responder, etc). The Thin Switch houses the Gen-Z Core Structure and several other key Gen-Z structures that define a singular Gen-Z component and enable end-to-end packet routing between the upper layer protocol engine(s) and the appropriate Link Layer Core (Gen-Z Interface).
The IPC-GZ201A-ZM Gen-Z Standard Switch Layer IP Core provides all of the features of the Thin Switch Layer IP Core. In addition, the Standard Switch Layer enables end-to-end packet relay between Link Layers.
The Gen-Z Thin and Standard Switch Layer IP Cores expose several synthesis time parameters and a memory-mapped register interface for static and dynamic configuration flexibility.
The IPC-GZ201A-ZM Gen-Z Thin Switch Layer IP Core provides a streaming interface to connect one or more IPC-GZ198A-ZM Gen-Z Link Layer IP Cores to one or more upper layer cores (Requester, Responder, etc). The Thin Switch houses the Gen-Z Core Structure and several other key Gen-Z structures that define a singular Gen-Z component and enable end-to-end packet routing between the upper layer protocol engine(s) and the appropriate Link Layer Core (Gen-Z Interface).
The IPC-GZ201A-ZM Gen-Z Standard Switch Layer IP Core provides all of the features of the Thin Switch Layer IP Core. In addition, the Standard Switch Layer enables end-to-end packet relay between Link Layers.
The Gen-Z Thin and Standard Switch Layer IP Cores expose several synthesis time parameters and a memory-mapped register interface for static and dynamic configuration flexibility.
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