English
USB 3.1 PHY (10G/5G) inTSMC (16nm, 12nm, N7, N6, N5,N3E, N3P)
You are here:
GF L40LP 40nm Deskew PLL - 300MHz-1500MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the clock reference by an integer between 1 and 4. It provides three 50% duty cycle skew aligned outputs that are divided down from the internal VCO frequency by 1, 2, and 4.
View GF L40LP 40nm Deskew PLL - 300MHz-1500MHz full description to...
- see the entire GF L40LP 40nm Deskew PLL - 300MHz-1500MHz datasheet
- get in contact with GF L40LP 40nm Deskew PLL - 300MHz-1500MHz Supplier
Deskew PLL IP
- TSMC CLN7FFLVT 7nm Deskew PLL - 300MHz-1500MHz
- TSMC GF Intel Samsung Deskew Frequency Synthesizer PLL
- TSMC CLN20SOC 20nm Deskew PLL - 700MHz-3500MHz
- Fractional-N Integer LC DESKEW PLLs in FDSOI FDX (GF22FDX SS28FDS ST28FD-SOI 22FDX 28FDS)
- TSMC CLN7FF 7nm Deskew PLL - 400MHz-2000MHz
- TSMC CLN28HPC 28nm Deskew PLL - 700MHz-3500MHz