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GSMC 0.18um 1.8V/3.3V Clockgating Cell Library
VeriSilicon GSMC 0.18um 1.8V/3.3V Clockgating Cell (01) Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corporation (GSMC) 0.18um Logic 1P6M Salicide 1.8/3.3V process. This library supports both latch posedge and latch negedge type clock gating cell with multiple drive strengths and with/without postcontrol test function. While satisfying the performance and power requirements, it was optimized for area efficiency.
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GSMC 0.18um 1.8V/3.3V Clockgating Cell Library IP
- SMIC 0.18um 1.8V/3.3V Clockgating Cell Library
- GSMC 0.18um 1.8V/3.3V DUP I/O Library
- VeriSilicon GSMC 0.18um 1.8V/3.3V Multiple I/O (05) Library
- GSMC 0.18um 9track Standard Cell Library, 1.8v operating voltage
- GSMC 0.18um 3.3V Standard Cell Library, 3.3v operating voltage
- GSMC 0.18um 1.8V<->3.3V Level Shifter Library, 1.8v/3.3v operating voltage