GSMC 0.18um VCC Detector

The present IP is a VCC Detector (VDT) circuit. It detects the voltage level of both core (AVDD18) and I/O (AVDD33). It will generate four flag signals，VDT18H, VDT18L, VDT33H and VDT33L, when AVDD18 and AVDD33 reach the trigger point. This IP contains four comparators and a reference voltage from external bandgap. The output may be in the wrong voltage level during the power-up phase before the bandgap becomes stable.

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