H.265 HEVC Decoder

The H.265 HEVC Decoder System IPr is a highly optimized and parameterisable IP Core targeted exclusively at Intel FPGA technology. It is an ultra-low latency solution that is extremely robust with excellent error concealment, compliant with the ITU-T H.265 standard, designed for applications ranging from High End Broadcast, Contribution and Medical applications through to consumer grade applications.
Korusys provide both the IP core and, as an Intel FPGA Design Solutions Network Partner, experienced Design Services surrounding the core to implement the most efficient solution for each customer application. The IPr can be provided as a standalone netlist solution for integration into a customer’s design, or it can be customized and scaled to a particular implementation. A simple API is provided to ease integration.
This IPr is available as just the IP Core or as a package with our High Performance FPGA PCIe Accelerator Card.

• see the entire H.265 HEVC Decoder datasheet
• get in contact with H.265 HEVC Decoder Supplier