H.265 Video Encoder/Decoder IP Core

The H265 HEVC video encoder IP core is a single-chip solution designed to support H.265 video encoding across various resolutions, including QVGA, SD, HD up to 1080p@120, and 4K@60, with future support planned for 8K@60. Currently, it supports up to 1080p@60 and 4K@60, and is compatible with FPGAs from both Xilinx and Intel, including the Xilinx Zynq-7000 and Intel Arria-10 series. The encoder supports Main 4:2:2 at 10 bits, with options for encoding 4:2:0 or 4:2:2 streams, and is available in 8-bit and 10- bit profiles, catering to both consumer products and high-end applications like broadcast and medical devices. It comes with a user API for controlling encoder operations, and is offered in various versions: Standard, I-Frame, Slim, and other specialized versions for multi-channel and 3D HD TV applications.

• see the entire H.265 Video Encoder/Decoder IP Core datasheet
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