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HBM3 PHY & Controller
SkyeChip’s High Bandwidth Memory (HBM) IP consists of a PHY and memory controller optimized for TSMC N7, N12 and Samsung 4nm process to support the HBM3 memory standard operating at up to 6.4 Gbps/pin. SkyeChip’s HBM IP is designed for high memory throughput and low latency applications while minimizing area and power consumption.
SkyeChip’s HBM IP is available either as a standalone HBM3 PHY that communicates with a memory controller over a modified variant of the DDR PHY Interface (DFI) 5.0 standard or as a combination of both the HBM3 PHY and the HBM3 memory controller as shown in Figure 1. The HBM3 PHY is provided as a hard HBM3 PHY IP that is primarily delivered as GDSII inclusive of its own PLL and the HBM3 I/Os. The HBM3 PHY is also equipped with a hardware-assisted embedded microcontroller that is responsible to train and optimize the channel timings of the memory interface. The hardware-assisted embedded microcontroller provides the flexibility to perform firmware-based training algorithms and interface tests.
SkyeChip’s HBM IP is available either as a standalone HBM3 PHY that communicates with a memory controller over a modified variant of the DDR PHY Interface (DFI) 5.0 standard or as a combination of both the HBM3 PHY and the HBM3 memory controller as shown in Figure 1. The HBM3 PHY is provided as a hard HBM3 PHY IP that is primarily delivered as GDSII inclusive of its own PLL and the HBM3 I/Os. The HBM3 PHY is also equipped with a hardware-assisted embedded microcontroller that is responsible to train and optimize the channel timings of the memory interface. The hardware-assisted embedded microcontroller provides the flexibility to perform firmware-based training algorithms and interface tests.
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