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HDMI 2.0b IP Core
The Bitec HDMI 2.0b IP Core enables HDMI interconnectivity without the need for external HDMI ASSP devices. Supporting pixel clocks to 600Mhz, the IP core allows ULTRA HD designs while using minimal device i/o pin resources. The core can operate in 1-, 2- and 4.symbols per clock allowing for high pixel rates on low end FPGA devices.
Used in over 600 million devices, HDMI represents the most common interconnect standard for high definition video and audio.
The Bitec HDMI 2.0b IP Core enables HDMI interconnectivity in FPGA or ASIC devices. Supporting pixel clocks to 600Mhz, the IP core allows ULTRA HD designs while using minimal device i/o pin resources. The core can operate in 1-, 2- or 4-symbols per clock allowing for high pixel rates on low end device technologies.
Both Video and Audio is supported with added low-level access to Auxiliary data packets. This feature allows low level development and testing of HDMI interfaces. It also allows a more flexible interface to the latest 3D and 4K video formats and control packets.
The core provides convenient interfacing to 3rd party SERDES for rapid development of image processing systems. It is also designed to operate in parallel with the Bitec DP 1.2 IP Core to achieve DP++ compatibility.
The IP Core has been interoperability tested at various CEA HDMI Plugfest events and is fully Certified.
Used in over 600 million devices, HDMI represents the most common interconnect standard for high definition video and audio.
The Bitec HDMI 2.0b IP Core enables HDMI interconnectivity in FPGA or ASIC devices. Supporting pixel clocks to 600Mhz, the IP core allows ULTRA HD designs while using minimal device i/o pin resources. The core can operate in 1-, 2- or 4-symbols per clock allowing for high pixel rates on low end device technologies.
Both Video and Audio is supported with added low-level access to Auxiliary data packets. This feature allows low level development and testing of HDMI interfaces. It also allows a more flexible interface to the latest 3D and 4K video formats and control packets.
The core provides convenient interfacing to 3rd party SERDES for rapid development of image processing systems. It is also designed to operate in parallel with the Bitec DP 1.2 IP Core to achieve DP++ compatibility.
The IP Core has been interoperability tested at various CEA HDMI Plugfest events and is fully Certified.
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