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HDMI 2.1 eARC RX PHY in TSMC (16nm, 12nm, N6)
The Synopsys HDMI 2.1 RX Controller and PHY IP solutions, compliant with the High-Definition Multimedia Interface (HDMI) 2.1 specification, provide the necessary logic to implement and verify designs for various HDMI-based
applications. The silicon-proven HDMI 2.1 IP provides quality digital video and audio transmission with up to 48Gbps aggregate bandwidth for uncompressed 8K resolution at 60Hz refresh rate. It supports the required features of HDMI
2.1 including dynamic HDR and enhanced audio return channel (eARC) and more, ensuring higher video quality and most advanced audio formats. The IP also supports latest HDMI 2.1a addition for Source based tone mapping.
The complete power- and area-optimized HDMI 2.1 RX IP solution encompasses a suite of configurable digital controllers, high-speed, mixed-signal PHYs, PLL, verification IP, High-bandwidth Digital Content Protection (HDCP) embedded security modules (ESMs), Display Stream
Compression (DSC) IP, all pre-integrated and shipped with a reference system. Having all necessary design blocks for the HDMI subsystem enables system- on-chip (SoC) designers to lower integration risk and accelerate time-to-market.
applications. The silicon-proven HDMI 2.1 IP provides quality digital video and audio transmission with up to 48Gbps aggregate bandwidth for uncompressed 8K resolution at 60Hz refresh rate. It supports the required features of HDMI
2.1 including dynamic HDR and enhanced audio return channel (eARC) and more, ensuring higher video quality and most advanced audio formats. The IP also supports latest HDMI 2.1a addition for Source based tone mapping.
The complete power- and area-optimized HDMI 2.1 RX IP solution encompasses a suite of configurable digital controllers, high-speed, mixed-signal PHYs, PLL, verification IP, High-bandwidth Digital Content Protection (HDCP) embedded security modules (ESMs), Display Stream
Compression (DSC) IP, all pre-integrated and shipped with a reference system. Having all necessary design blocks for the HDMI subsystem enables system- on-chip (SoC) designers to lower integration risk and accelerate time-to-market.
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