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HDMI2.0/1.4 RX PHY & Controller
Innosilicon HDMI RX IP is designed to receive and recover the video and audio data from a HDMI source device for display applications, which is compatible with HDMI2.0, HDMI1.4 and DVI1.0 specifications.
Innosilicon HDMI RX IP is composed of the controller, the physical layer and the PHY logic.
The controller supports major display formats up to 4K * 2K resolution, including 3D formats and common DTV and graphic display application, with true color or deep color resolutions.
The video interface can generate a variety of video formats, including RGB 4:4:4, YCbCr 4:4:4, YCbCr 4:2:2 and YCbCr 4:2:0. These formats are supported in both SDR and DDR modes.
The audio interface includes up to four I2S output, four S/PDIF output and a parallel audio output, supporting for HDMI 2.0 audio formats.
The optional decryption engine follows the High-bandwidth Digital Content Protection (HDCP) system 2.2 specification, and enables the content protection mechanisms included in the HDMI specification.
The integrated I2C slave interface is provided for implementing the HDCP authentication mechanism.
The RX digital core is designed to interface with Innosilicon RX PHY, enabling the integration of a complete HDMI 2.0 RX interface, and avoiding the cost and complexity of external discrete solutions.
The HDMI receiver controller separates the incoming data stream into audio data, video data, and packet data information. It configures itself automatically based on the packet data information received, with no software intervention. Users can also configure it manually by using the register interface.
The physical layer contains 3 data channels, a clock channel, PLL and bias circuit.
The data channels consist of termination, level-shifter and equalizer circuit. In each data channel, the termination provides common mode voltage and termination resistance for the differential pair at the receiver end. The level-shifter changes the common mode voltage of input signals from the termination supply domain to a proper level that satisfies the input voltage range of equalizer. The input signals are reshaped by equalizer for frequency compensation. Then the serial stream is recovered and converted to 10-bit parallel output.
The clock channel receives the TMDS clock with the frequency up to 594MHz. The 3 data channels receive TMDS data to form a TMDS link in combination with the clock channel.
The PLL generates the clocks required by data channels and the digital logic.
The bias circuit generates voltage and current reference.
The PHY logic receives the recovered parallel data and clock signals. These data are firstly synchronized to the same clock, then aligned to eliminate the channel skew and finally output to the controller for further process.
Innosilicon HDMI RX IP offers reliable implementation for HDMI interface, which can be integrated in the SoC used in multimedia devices.
Innosilicon HDMI RX IP is composed of the controller, the physical layer and the PHY logic.
The controller supports major display formats up to 4K * 2K resolution, including 3D formats and common DTV and graphic display application, with true color or deep color resolutions.
The video interface can generate a variety of video formats, including RGB 4:4:4, YCbCr 4:4:4, YCbCr 4:2:2 and YCbCr 4:2:0. These formats are supported in both SDR and DDR modes.
The audio interface includes up to four I2S output, four S/PDIF output and a parallel audio output, supporting for HDMI 2.0 audio formats.
The optional decryption engine follows the High-bandwidth Digital Content Protection (HDCP) system 2.2 specification, and enables the content protection mechanisms included in the HDMI specification.
The integrated I2C slave interface is provided for implementing the HDCP authentication mechanism.
The RX digital core is designed to interface with Innosilicon RX PHY, enabling the integration of a complete HDMI 2.0 RX interface, and avoiding the cost and complexity of external discrete solutions.
The HDMI receiver controller separates the incoming data stream into audio data, video data, and packet data information. It configures itself automatically based on the packet data information received, with no software intervention. Users can also configure it manually by using the register interface.
The physical layer contains 3 data channels, a clock channel, PLL and bias circuit.
The data channels consist of termination, level-shifter and equalizer circuit. In each data channel, the termination provides common mode voltage and termination resistance for the differential pair at the receiver end. The level-shifter changes the common mode voltage of input signals from the termination supply domain to a proper level that satisfies the input voltage range of equalizer. The input signals are reshaped by equalizer for frequency compensation. Then the serial stream is recovered and converted to 10-bit parallel output.
The clock channel receives the TMDS clock with the frequency up to 594MHz. The 3 data channels receive TMDS data to form a TMDS link in combination with the clock channel.
The PLL generates the clocks required by data channels and the digital logic.
The bias circuit generates voltage and current reference.
The PHY logic receives the recovered parallel data and clock signals. These data are firstly synchronized to the same clock, then aligned to eliminate the channel skew and finally output to the controller for further process.
Innosilicon HDMI RX IP offers reliable implementation for HDMI interface, which can be integrated in the SoC used in multimedia devices.
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