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HDMI2.0 Receiver PHY
Innosilicon HDMI RX IP is designed to receive and recover the video and audio data from an HDMI source device for display applications.
Innosilicon HDMI RX IP is composed of the physical layer and the PHY logic. The physical layer contains 1 clock channel, 3 data channels, and bias circuit. The clock channel consists of termination, level-shifter and PLL circuit. The data channel consists of termination, level-shifter, equalizer and CDR circuit.
In each data channel, the termination provides common mode voltage and termination resistance for the differential pair at the receiver end. The level-shifter changes the common mode voltage of input signals from the termination supply domain to a proper level that satisfies the input voltage range of equalizer. The input signals are reshaped by equalizer for frequency compensation. Then the serial stream is recovered by CDR and converted to parallel output.
The PHY logic receives the recovered parallel data and clock signals of 3 data channels. These data are firstly synchronized to the same clock, then aligned to eliminate the channel skew and finally output to the controller for further process.
Innosilicon HDMI RX IP offers reliable implementation for HDMI interface, which can be integrated in the SOC used in multimedia device.
Innosilicon HDMI RX IP is composed of the physical layer and the PHY logic. The physical layer contains 1 clock channel, 3 data channels, and bias circuit. The clock channel consists of termination, level-shifter and PLL circuit. The data channel consists of termination, level-shifter, equalizer and CDR circuit.
In each data channel, the termination provides common mode voltage and termination resistance for the differential pair at the receiver end. The level-shifter changes the common mode voltage of input signals from the termination supply domain to a proper level that satisfies the input voltage range of equalizer. The input signals are reshaped by equalizer for frequency compensation. Then the serial stream is recovered by CDR and converted to parallel output.
The PHY logic receives the recovered parallel data and clock signals of 3 data channels. These data are firstly synchronized to the same clock, then aligned to eliminate the channel skew and finally output to the controller for further process.
Innosilicon HDMI RX IP offers reliable implementation for HDMI interface, which can be integrated in the SOC used in multimedia device.
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