English
You are here:
HDMI2.1 TX PHY
Innosilicon HDMI TX PHY IP is designed for transmitting video and audio data from a video source device to a display device, which is compatible with HDMI2.1, HDMI2.0, HDMI1.4, and DVI1.0 specifications. The video resolution supports up to 8k@60Hz.
Innosilicon HDMI TX PHY IP consists of a digital logic and a physical layer.
The digital logic receives video, audio, synchronous signals, and control signals from the controller and outputs encoded data to the physical layer.
The physical layer contains 4 data channels, PLL, and bias circuit. Each data channel consists of a serializer and a driver. The serializer converts the parallel input data to 1-bit high speed serial stream and the driver converts the digital serial data to low swing differential signals with typical DC-coupled connection. The data rate is up to 12Gbps per channel. In HDMI2.0 and HDMI1.4 modes, one data channel serves as the clock channel and transmits clock signal up to 340MHz to the receiver, and the other 3 data channels transmit data signal up to 6Gbps. PLL generates the clocks required by data channels and the digital logic. The bias circuit generates voltage and current reference.
Innosilicon HDMI TX PHY IP offers reliable implementation for HDMI interface, which can be integrated in the SoC used in multimedia devices.
Innosilicon HDMI TX PHY IP consists of a digital logic and a physical layer.
The digital logic receives video, audio, synchronous signals, and control signals from the controller and outputs encoded data to the physical layer.
The physical layer contains 4 data channels, PLL, and bias circuit. Each data channel consists of a serializer and a driver. The serializer converts the parallel input data to 1-bit high speed serial stream and the driver converts the digital serial data to low swing differential signals with typical DC-coupled connection. The data rate is up to 12Gbps per channel. In HDMI2.0 and HDMI1.4 modes, one data channel serves as the clock channel and transmits clock signal up to 340MHz to the receiver, and the other 3 data channels transmit data signal up to 6Gbps. PLL generates the clocks required by data channels and the digital logic. The bias circuit generates voltage and current reference.
Innosilicon HDMI TX PHY IP offers reliable implementation for HDMI interface, which can be integrated in the SoC used in multimedia devices.
View HDMI2.1 TX PHY full description to...
- see the entire HDMI2.1 TX PHY datasheet
- get in contact with HDMI2.1 TX PHY Supplier