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MIPI C-PHY/D-PHY Combo CSI-2 RX+ IP (6.0Gsps/trio, 4.5Gbps/lane) in TSMC N6
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High Bandwidth Memory (HBM2E) HBM2E PHY for TSMC N7
Optimized for the low-latency and high-bandwidth memory applications, the HBM Gen2 PHY delivers maximum performance and flexibility
HBM is a high-performance memory that features reduced power consumption and a small form factor. It combines 2.5D packaging with a wider interface at a lower clock speed (as compared to DDR4) to deliver higher overall throughput at a higher bandwidth-per-watt efficiency for high-performance computing applications. The Cadence HBM Gen2 PHY is fully compliant to the JEDEC HBM2 standard and supports data rates up to 3200 Mbps per data pin, resulting in a total bandwidth of 410 GB/s. The interface features 8 independent channels, each containing 128 bits for a total data width of 1024 bits, and support for a stack height of 2, 4 or 8 DRAMs. In addition, the PHY is designed for a 2.5D system with an interposer for routing signals between the DRAM and PHY. This combination of signal density and stacked form factor requires special design consideration. In order to enable easy implementation and improved flexibility of design in such a complex system, Cadence performs complete signal and power integrity analysis on the entire 2.5D system to ensure that all signal, power and thermal requirements are met.
HBM is a high-performance memory that features reduced power consumption and a small form factor. It combines 2.5D packaging with a wider interface at a lower clock speed (as compared to DDR4) to deliver higher overall throughput at a higher bandwidth-per-watt efficiency for high-performance computing applications. The Cadence HBM Gen2 PHY is fully compliant to the JEDEC HBM2 standard and supports data rates up to 3200 Mbps per data pin, resulting in a total bandwidth of 410 GB/s. The interface features 8 independent channels, each containing 128 bits for a total data width of 1024 bits, and support for a stack height of 2, 4 or 8 DRAMs. In addition, the PHY is designed for a 2.5D system with an interposer for routing signals between the DRAM and PHY. This combination of signal density and stacked form factor requires special design consideration. In order to enable easy implementation and improved flexibility of design in such a complex system, Cadence performs complete signal and power integrity analysis on the entire 2.5D system to ensure that all signal, power and thermal requirements are met.
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