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High-performance and power-efficient processor core based on RISC-V Instruction Set Architecture (ISA)
Features
- Customization For Domain-Specific Needs
- Compatible with standard RISC-V instruction set and allow for certain extensions
- Catering to various target application needs, by optimizing the performance, power dissipation and PPA; supporting on-demand configuration of processor core’s major functionality, SoC system-level IPs, interfaces and other IPs.
- Optimization of Energy Efficiency by Adopting Multiple Layers of Low Power Design
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RISC-V IP
- RISC-V ARC-V RMX-100 Ultra-low Power 32-bit Processor IP for Embedded Applications
- ARC-V RMX-500 power efficient 32-bit RISC-V processor for embedded applications
- ARC-V RHX-105 dual-issue, 32-bit RISC-V processor for real-time applications (multi-core)
- 32-bit Embedded RISC-V Functional Safety Processor
- 64-bit RISC-V Application Processor Core
- Dual-issue Linux-capable RISC-V core