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High Performance SHA-1 Hash Core for Xilinx FPGA
Features
- Implements the SHA-1 secure hash algorithm to NIST FIPS Publication 180-1
- Fast operation - each 512-bit block requires 81 master clock cycles (1 clock per algorithm step + 1 clock load)
- Performs automatic message length calculation and padding insertion
- Optional user initialisation of IVs for efficient HMAC support
- Simple external interface
- Highly optimised for use in Xilinx FPGA
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