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High performance three-issue, out-of-order RISC-V vector application processor
The SiFive Performance™ P500 application processor features a thirteen-stage, triple-issue, out-of-order pipeline compatible with the RISC-V RV64GBC ISA. The Performance P500 scales up to four-core complex configurations while delivering 30% higher performance in less than half the area of a comparable Arm® Cortex®-A75.
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Block Diagram of the High performance three-issue, out-of-order RISC-V vector application processor
CPU IP
- High Bandwidth Out-of-Order RISC-V CPU IP Core
- Compact, low-power 32-bit RISC CPU
- High-performance 32-bit RISC CPU
- All in one solution for AI in RISC-V
- 2D (vector graphics) GPU IP Further advanced architecture for minimized CPU load and increased pixel performance in vector processing
- 2D (vector graphics) & 3D GPU IP A GPU IP combining 3D and 2D rendering features with high performance, low power consumption, and minimum CPU load